U.S. Pat. No. 5,606,566 describes a circuit test technique that uses the IEEE1149.1 test standard. A circuit contains a plurality of integrated circuits with functional interconnections to communicate signals between the integrated circuits during normal operation. The circuit is tested by entering test signal into the circuit and observing how the circuit responds to the test data. The interconnections between the integrated circuits, for example, are tested by applying test signals at the output of the integrated circuits and observing whether corresponding response signals arrive at the inputs of the integrated circuits.
The IEEE1149.1 standard, as described in U.S. Pat. No. 5,606,566 defines a test interface for entering the test signals into the circuit and reading the response signals from the circuit. A one-bit wide shift structure is used for this purpose. The integrated circuits are connected in a chain of successive integrated circuit. Each integrated circuit has one test data input terminal coupled to its predecessor in the chain, if any, and one test data output coupled to its successor in the chain, if any. In addition the integrated circuits have test clock and test mode select inputs coupled in common.
Successive bits of the test signals are applied to the test data input of the chain and shifted from integrated circuit to integrated circuit in the chain to the integrated circuit from where the test signal is output to test the functional interconnections. Similarly, the response signals are loaded into the integrated circuit from the functional interconnections and successive bits of the response signals are shifted from integrated circuit to integrated circuit in the chain to a test data output. Control instructions are similarly shifted through the chain. Shifting, outputting and loading is synchronized by a central clock that is coupled to the test clock inputs of the integrated circuits and controlled by a mode select signal that is coupled to the test mode select inputs of the integrated circuits. The mode select signal controls how the test interface traverses a state diagram of the test interface.
The IEEE1149.1 standard is based on a compromise between access speed and pin/connection count. Only two test data pins are needed per integrated circuit, and only one test data connection to another integrated circuit. In return, it takes a long time to write or read test data, because the data and instructions have to pass through a chain of integrated circuits.
Various techniques have been proposed to increase the access speed of IEEE1149.1 interfaces U.S. Pat. No. 5,606,566, for example, proposes to use several chains in parallel. A method of improving speed is of course to increase the speed of the test clock. But there are limits to the maximum clock speed, not only in terms of maximum internal speed of the integrated circuits, but also due differences between the delays introduced by the connections from the central clock source to the different integrated circuits. The differences between these delays are referred to as clock skew. These should not exceed the length of the clock period.